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[VHDL-FPGA-Verilog] riscmcu

Description: 精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
Platform: | Size: 79872 | Author: 磊 | Hits:

[OS Develop] minirisc.tar

Description: verilog code .descrip the risc cpu.download from opencores.org-verilog code. descrip the risc cpu.download from opencores.org
Platform: | Size: 74752 | Author: 刘科麟 | Hits:

[VHDL-FPGA-Verilog] RiscCPU8

Description: 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
Platform: | Size: 219136 | Author: hulin | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[VHDL-FPGA-Verilog] RiscCpu

Description: 4位RISC指令CPU源码,需要的朋友可以看看!-4 RISC instructions CPU source, can look at the Friend in need!
Platform: | Size: 9216 | Author: 陈谦 | Hits:

[VHDL-FPGA-Verilog] RISC8.ZIP

Description: verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
Platform: | Size: 80896 | Author: likui | Hits:

[VHDL-FPGA-Verilog] OR1200_verilog

Description: or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog description of the risc cpu realize, cpu source code analysis and chip design source book
Platform: | Size: 204800 | Author: yu | Hits:

[Other] risc

Description: 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
Platform: | Size: 1259520 | Author: xu | Hits:

[VHDL-FPGA-Verilog] computer12

Description: 基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
Platform: | Size: 64512 | Author: steven | Hits:

[VHDL-FPGA-Verilog] 8risc

Description: 8位RISC CPU,包括alu,count,machine-8 bit risc cpu
Platform: | Size: 3072 | Author: 刘成诚 | Hits:

[VHDL-FPGA-Verilog] soc-gr0040-010309

Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Platform: | Size: 406528 | Author: urga turg | Hits:

[VHDL-FPGA-Verilog] lariviere2008uclinux

Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Platform: | Size: 252928 | Author: urga turg | Hits:

[DSP program] risc_cpu

Description: This an example of simple RISC CPU implemented in SystemC.-This is an example of simple RISC CPU implemented in SystemC.
Platform: | Size: 41984 | Author: R Zhang | Hits:

[Software Engineering] CPU_Architecture

Description: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism. -Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
Platform: | Size: 2506752 | Author: Amit Adoni | Hits:

[VHDL-FPGA-Verilog] CPU_Architecture

Description: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism. -Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
Platform: | Size: 2388992 | Author: Amit Adoni | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] 8bit_RISC_CPU_RTL_Code

Description: 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
Platform: | Size: 79872 | Author: 曾亮 | Hits:

[Other Embeded program] RISCCPU

Description: 简单的CPU设计流程PPT，用于教学目的，可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
Platform: | Size: 156672 | Author: 柳泽明 | Hits:

[Windows Develop] mipscpu-source

Description: mips cpu的实现.MIPS是世界上很流行的一种RISC处理器。MIPS公司的R系列就是在此基础上开发的RISC工业产品的微处理器。这些系列产品为很多计算机公司采用构成各种工作站和计算 机系统。 -mips cpu implementation. MIPS is the world' s very popular as a RISC processor. MIPS company' s R series is based on the development of industrial products RISC microprocessor. These series of products for many computer companies used to create various workstations and computer systems.
Platform: | Size: 7025664 | Author: 汤龑鸣 | Hits:
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